The present invention generally relates to image signal processing systems for encoding an image signal into an encoded signal and/or for decoding the encoded signal at a high speed into the original image signal, and, more particularly, to a high-speed image signal processing system which can be suitably applied to a facsimile apparatus to encode a bit map image signal for use in the facsimile apparatus into an encoded signal at a high speed and/or to decode the encoded signal into the original image signal.
As a prior art image signal processing systems for encoding an image signal into an encoded signal and/or for decoding the encoded signal at a high speed into the original image signal, several types of systems which follow are known.
In first one of the types of the prior art systems as disclosed, for example, in JP-A-49-126368, in a signal transmission mode, an image signal obtained from a reader is converted at a high-quality converter into a binary image signal by a scanning image processor and then temporarily stored in a bit map page memory connected directly to an image bus. Next, the binary image signal stored in the bit map page memory is encoded at an encoder/decoder unit connected directly to a system bus into an encoded signal, and the encoded signal is then stored in an encoded-document memory connected directly to the system bus. Subsequently the encoded signal stored in the encoded-document memory is, as necessary, transmitted through a communication unit connected directly to the system bus.
In a signal reception mode, on the other hand, an encoded signal received at the communication unit is temporarily stored in the encoded-document memory through the system bus. The encoded signal temporarily stored in the encoded-document memory is then decoded at the encoder/decoder unit through the system bus into a binary image signal and stored in the bit map page memory through the image bus. Next, the binary image signal stored in the bit map page memory is converted into an image signal by a recording signal processor connected directly to the image bus to be recorded at a recorder.
The second type of prior art system is disclosed in, for example, an article entitled "ASIC Introduction in Ultra-high Speed Facsimile Apparatus" in a magazine ELECTRONIC TECHNIQUES, 1988, April, pp. 64-72.
This literature is different from the above invention of JP-A-59-126368 in that, in this literature, the encoder/decoder unit of the above invention is separated into an encoder and a decoder and the bit map page memory is removed.
The operation of the second type of system is substantially the same as that of the above first type of system, except that the binary image signal is sent from the scanning signal processor directly to the encoder to be encoded thereat and that the binary image signal decoded at the decoder is sent directly to the recording signal processor.
A third type of prior art system is disclosed, for example, in JP-A-57-57084, in which a facsimile apparatus employing a constant-speed recorder (such as a laser printer), a bit map page memory is provided for storing therein a bit map document image signal obtained through the decoding operation of a received encoded signal, the memory being required to have a storage capacity of one or more pages.
in the first type system, it is necessary, in the transmission and reception modes, to transfer the same binary image signal twice through the image bus and to transfer the same encoded signal twice through the system bus during one-page processing operation. Thus, when it is desired to carry out the transmitting and receiving operations at the same time, the same signal must be transferred four times through each of the image and system buses. For this reason, in order to realize a higher-speed and higher-function system, this disadvantageously involves the need for such a bus that can be operated at a higher speed. Further, the first type system has another problem in that the bit map page memory must have such a large capacity as to be able to store pixels corresponding to one or more document pages, and since the bit map page memory comprises a semiconductor memory for its high speed operation, the cost of the entire system is unfavorably made high.
Meanwhile, the second type system has a problem that it is necessary, even in the transmission and reception modes, to transfer the same encoded signal twice through the system bus during one-page processing operation. Thus, like the first type system, such a system bus as to be-able to be operated at a higher speed becomes necessary.
In the second type system, further, since the encoding and decoding operations are carried out directly without any intervention of any bit map page memory, it becomes necessary to transfer the encoded signal from the encoder to the encoded-document memory through the system bus in conformity with the reading rate or to transfer the encoded signal from the encoded-document memory to the decoder through the system bus in conformity with the recording rate. In this way, this system is disadvantageous in that the load on the system bus due to the transfer of the encoded signal becomes high and thus it is difficult to make high the reading and recording speeds.
The third type system has a problem that the bit map page memory must have a large capacity.
In facsimile techniques, in order to improve an image-data transmission efficiency, image data transmission is carried out on such a Modified Huffman (MH), modified READ (MR) or modified MR (MMR) coding basis as recommended by Comite Consultatif International Telegraphique et Telephonique (CCITT). In this coding, the image data is transmitted in the form of codes to which white-black transition points in the image data are converted, that is, when the code conversion is carried out for the same data bit number and the number of white-black transition points per unit length of the data is relatively large, the amount of processing of the data is correspondingly increased, which results in the data encoding rate also being decreased. The same hold true when it is desired to decode the encoded data. That is, when decoding is carried out for the same code bit number and the number of white-black transition points per unit length of the original data is relatively large, the number of bits in the data to be decoded is decreased.
To eliminate the above problem, there have been recently developed facsimile apparatuses which, even when it is desired to process such data having many white-black transition points as mentioned above, can perform its encoding and decoding operations at a high speed. One example of such facsimile apparatuses is disclosed in JP-A-60-194670 or JP-A-62-35780.
However, when this entire facsimile system including the encoding/decoding means is observed, a control unit, a memory means, a reader means, a recorder means, an encoder means and a decoder means in the system are operated as closely associated with each other. Accordingly, it is clear that, without consideration of transfer of control signals between these peripheral devices and the load state of a data bus, it is impossible to form an efficient facsimile system.
This type of facsimile system is disclosed, as an example, in a magazine ELECTRONIC TECHNIQUES, 1988, April, pp. 64-72 and in the same magazine, 1990, August, pp. 67-71. In this facsimile system, no reference is made to how to increase the efficiency of the encoding/decoding means.
In the high-speed encoding and decoding means of the aforementioned literature there is disclosed making the facsimile system in the form of a gate array to reduce the number of necessary parts. Thus, no consideration is paid to how to improve the method of transferring the control signals among the encoder means, control unit and reader means and the method for transferring the control signals among the decoder means, control unit and recorder means to provide high-speed processing with use of a smaller number of necessary parts in the entire facsimile system.
For this reason, in the case where the aforementioned high-speed encoder/decoder means are built in the facsimile system, the control load of the control unit over the encoder/decoder means becomes too high. Accordingly, without employing a processor having a high processing ability as the control unit or without adding a means for increasing the number of processors, the system cannot fully exhibit the high-speed processing performance of the encoder/decoder means. In this case, in addition, when it is desired to improve the user application service of the entire facsimile system with use of a prior art type of processor, the processing load of the control unit becomes too high and thus satisfactory service cannot be attained.
Further, even in the aforementioned facsimile apparatuses, since the control unit controls the operation start and end timing of respective parts, when it is desired to increase the data processing rate of the encoder/decoder means, this also involves excessively increasing the processing load of the control unit, whereby a satisfactory data processing rate cannot be attained.
For the purpose of increasing the data processing rate of the encoder/decoder means and improving the user application service, it has been proposed to employ a processor having a high processing ability or to increase the number of processors. However, this also undesirably involves an increase in the cost corresponding to the increased number or processors.